Field of the Invention
The invention lies in the semiconductor processing field. More specifically, the invention relates to an etching process for a two-layer metallization or dual damascene patterning for a semiconductor structure having functional elements formed in a substrate, a dielectric situated on the substrate, for example an oxide layer, and the etching mask comprising a photoresist and a polymer intermediate layer being inserted between the etching mask and the oxide layer.
Semiconductor structures are generally equipped with a multilevel metallization with corresponding interconnects which are connected via vertical intermediate connections to one another and/or to active or doped elements of the semiconductor structure. The interconnects and the intermediate connections are fabricated in a plurality of process steps which comprise deposition, patterning and etching steps.
A customary method for fabricating a two-level metallization consists firstly in fabricating a connection to individual functional elements of the semiconductor structure. To that end, with the aid of a photolithographic process followed by an etching step, an opening is produced through the oxide layer situated on the semiconductor structure, thereby defining the position of the intermediate connection in the first metallization plane. This opening, which extends vertically through the semiconductor structure, is subsequently filled with a thin adhesion layer, e.g. titanium nitride, and a metal, e.g. tungsten, in a deposition process, e.g. a CVD or sputtering method. Since the deposition process cannot be limited just to the opening, rather deposition is effected on the entire surface of the semiconductor structure, the excess metal on the surface must be removed for example by means of a so-called CMP process (chemical mechanical polishing) or by etching-back. Afterward, a metallization, e.g. made of aluminum, is applied on the oxide layer present and is then patterned photolithographically in order to produce the desired interconnect structure. That is done by applying a photoresist from which a photoresist etching mask is formed photolithographically, so that etching can then be effected through the etching mask and, finally, the interconnects remain.
In a preferred variant, an oxide layer is applied over the whole area in a planar manner and the negative of the interconnects is produced in the oxide layer by firstly applying a photoresist on the latter, which photoresist is then patterned photolithographically. Afterward, the negative structure of the interconnects is etched into the oxide layer through the openings in the photoresist. In a further step, the negative structure is then filled with a liner and then with a metal, e.g. aluminum or copper. The excess metal is then likewise removed by means of a CMP process step.
U.S. Pat. No. 5,801,094, by way of example, describes a dual damascene method wherein the metallization of the intermediate connections between structural elements of the semiconductor structure and an interconnect plane and the metallization of the interconnects of the interconnect plane are effected in one step. However, the preparatory method steps are still complicated. Thus, firstly an oxide layer as dielectric is applied on the substrate and then an etching stop layer is applied. Openings are etched into the etching stop layer at the locations at which intermediate connections are to be realized, after the photolithographic application of an etching mask, with the result that the underlying oxide layer is uncovered. A further oxide layer as carrier for the interconnects of a metallization plane is then applied on the etching stop layer. The patterning of the negative form of the interconnects within the upper oxide layer and of the negative form for the intermediate connections is effected with the aid of photolithography and subsequent etching. During the etching operation, openings are etched into the upper oxide layer in accordance with the etching mask either until the etching stop layer is reached or, at the locations where the etching stop layer is interrupted for the realization of the intermediate connections in the via, as far as the underlying interconnects to be contact-connected or as far as the substrate (self-aligned dual damascene).
After the removal of the etching mask, the metallization can then be effected by filling the trenches for the interconnects and also the openings for the intermediate connections simultaneously with metal, metal also being deposited on the rest of the surface. Accordingly, the surface must also be planarized afterward, e.g. by means of a CMP (chemical mechanical polishing) process.
Furthermore, a method is known wherein the intermediate connections are patterned in a first process step (photolithography and etching process) and the interconnects are formed in a subsequent process step (photolithography and etching process) (sequential dual damascene). A photolithography method is used for this as standard, wherein method an intermediate layer made of a polymer, i.e. an ARC polymer as antireflection layer, is inserted below the photoresist layer in order to preclude reflections during the exposure of the photoresist and hence to minimize the reflected light and thereby to improve the resolution. This involves a standard photo-process for sub-0.5 mm technologies with DUV (deep ultraviolet) exposure. Antireflection layers of this type may comprise organic or inorganic materials.
However, in the process—which is effected after the photolithographic step for forming the etching mask—of etching for the purpose of opening the oxide layer in order to form e.g. a trench, this intermediate layer leads to problems. The ARC polymer layer is not opened during the photolithographic process. Therefore, the etching process for patterning the interconnects must begin with an ARC etching step (polymer etch). The second step is then the oxide etching step (normal two-step process). The problem here is that the contact holes that have already been opened are/have been filled with the ARC polymer.
In this case, fence formation is unavoidable. A fence is to be understood as a comparatively sharp-edged rim which projects as residue of the intermediate layer and at least partly surrounds the opening etched into the oxide layer. However, during a subsequent metallization step, such fences make it more difficult to fill the trench and enable mechanical stresses to proceed from the fences. In particular, such fences are a disturbance during Al deposition by sputtering.
It has previously been attempted to avoid fence formation through an increased addition of oxygen during the interconnect etching process, as a result of which the build-up of a protective sidewall polymer layer can be suppressed. On the other hand, at the same time the photoresist sidewall is no longer passivated to a sufficient extent as a result, with the consequence that the critical dimension is widened. Another solution approach would be to employ hard mask patterning, but this is impracticable owing to the increased process complexity.